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? 2005 fairchild semiconductor corporation ds010992 www.fairchildsemi.com may 1992 revised march 2005 74abt244 octal buffer/line driver with 3-state outputs 74abt244 octal buffer/line driver with 3-state outputs general description the abt244 is an octal buffer and line driver with 3-state outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. features non-inverting buffers output sink capability of 64 ma, source capability of 32 ma guaranteed output skew guaranteed multiple output switching specifications output switching specified for both 50 pf and 250 pf loads guaranteed simultaneous switching, noise level and dynamic threshold performance guaranteed latchup protection high impedance glitch free bus loading during entire power up and power down cycle nondestructive hot insertion capability disable time less than enable time to avoid bus conten- tion ordering code: device also available in tape and reel. specify by appending suffix letter ?x? to the ordering code. pb-free package per jedec j-std-020b. note 1: ?_nl? indicates pb-free package (per jedec j-std-020b). device available in tape and reel only. order number package package description number 74abt244csc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74abt244csj m20d pb-free 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74abt244cmsa msa20 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide 74abt244cmsax_nl (note 1) msa20 pb-free 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide 74abt244cmtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74abt244cmtcx_nl (note 1) mtc20 pb-free 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74abt244cpc n20a 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide
www.fairchildsemi.com 2 74abt244 connection diagram pin descriptions truth table h high voltage level l low voltage level x immaterial z high impedance pin names description oe 1 , oe 2 output enable input (active low) i 0 ? i 7 inputs o 0 ? o 7 outputs oe 1 i 0?3 o 0?3 oe 2 i 4?7 o 4?7 hxzhxz lhhlhh llllll
3 www.fairchildsemi.com 74abt244 absolute maximum ratings (note 2) recommended operating conditions note 2: absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. functional operation under these conditions is not implied. note 3: either voltage limit or current limit is sufficient to protect inputs. dc electrical characteristics note 4: for 8 bits toggling, i ccd 0.8 ma/mhz. note 5: guaranteed, but not tested. storage temperature 65 q c to 150 q c ambient temperature under bias 55 q c to 125 q c junction temperature under bias 55 q c to 150 q c v cc pin potential to ground pin 0.5v to 7.0v input voltage (note 3) 0.5v to 7.0v input current (note 3) 30 ma to 5.0 ma voltage applied to any output in the disabled or power-off state 0.5v to 5.5v in the high state 0.5v to v cc current applied to output in low state (max) twice the rated i ol (ma) dc latchup source current 500 ma over voltage latchup (i/o) 10v free air ambient temperature 40 q c to 85 q c supply voltage 4.5v to 5.5v minimum input edge rate ( ' v/ ' t) data input 50 mv/ns enable input 20 mv/ns symbol parameter min typ max units v cc conditions v ih input high voltage 2.0 v recognized high signal v il input low voltage 0.8 v recognized low signal v cd input clamp diode voltage 1.2 v min i in 18 ma v oh output high voltage 2.5 v min i oh 3 ma 2.0 v min i oh 32 ma v ol output low voltage 0.55 i ol 64 ma i ih input high current 1 p amaxv in 2.7v (note 5) 1v in v cc i bvi input high current breakdown test 7 p amaxv in 7.0v i il input low current 1 p amax v in 0.5v (note 5) 1v in 0.0v v id input leakage test 4.75 v 0.0 i id 1.9 p a all other pins grounded i ozh output leakage current 10 p a0 5.5v v out 2.7v; oe n 2.0v i ozl output leakage current 10 p a0 5.5v v out 0.5v; oe n 2.0v i os output short-circuit current 100 275 ma max v out 0.0v i cex output high leakage current 50 p amaxv out v cc i zz bus drainage test 100 p a0.0v out 5.5v; all others gnd i cch power supply current 50 p a max all outputs high i ccl power supply current 30 ma max all outputs low i ccz power supply current 50 p amaxoe n v cc , all others at v cc or ground i cct additional i cc /input outputs enabled 2.5 ma max v i v cc 2.1v outputs 3-state 2.5 ma enable input v i v cc 2.1v outputs 3-state 50 p a data input v i v cc 2.1v all others at v cc or ground i ccd dynamic i cc no load ma/ max outputs open (note 5) 0.1 mhz oe n gnd, (note 4) one bit toggling, 50% duty cycle
www.fairchildsemi.com 4 74abt244 dc electrical characteristics (soic package) note 6: max number of outputs defined as (n). n 1 data inputs are driven 0v to 3v. one output at low. guaranteed, but not tested. note 7: max number of data inputs (n) switching. n 1 inputs switching 0v to 3v. input-under-test switching: 3v to threshold (v ild ), 0v to threshold (v ihd ). guaranteed, but not tested. note 8: max number of outputs defined as (n). n 1 data inputs are driven 0v to 3v. one output high. guaranteed, but not tested. ac electrical characteristics (soic and ssop package) extended ac electrical characteristics (soic package) note 9: this specification is guaranteed but not tested. the limits apply to propagation delays for all paths described switching in ph ase (i.e., all low-to-high, high-to-low, etc.). note 10: this specification is guaranteed but not tested. the limits represent propagation delay with 250 pf load capacitors in place of the 50 pf load capacitors in the standard ac load. this specification pertains to single output switching only. note 11: this specification is guaranteed but not tested. the limits represent propagation delays for all paths described switching in p hase (i.e., all low-to-high, high-to-low, etc.) with 250 pf load capacitors in place of the 50 pf load capacitors in the standard ac load. note 12: the 3-state delays are dominated by the rc network (500 : , 250 pf) on the output and have been excluded from the datasheet. conditions symbol parameter min typ max units v cc c l 50 pf, r l 500 : v olp quiet output maximum dynamic v ol 0.5 0.8 v 5.0 t a 25 q c (note 6) v olv quiet output minimum dynamic v ol 1.3 0.8 v 5.0 t a 25 q c (note 6) v ohv minimum high level dynamic output voltage 2.7 3.1 v 5.0 t a 25 q c (note 8) v ihd minimum high level dynamic input voltage 2.0 1.5 v 5.0 t a 25 q c (note 7) v ild maximum low level dynamic input voltage 1.1 0.8 v 5.0 t a 25 q c (note 7) t a 25 q ct a 55 q c to 125 q ct a 40 q c to 85 q c symbol parameter v cc 5v v cc 4.5v ? 5.5v v cc 4.5v ? 5.5v units c l 50 pf c l 50 pf c l 50 pf min typ max min max min max t plh propagation delay 1.0 2.5 3.6 1.0 5.3 1.0 3.6 ns t phl data to outputs 1.0 2.3 3.6 1.0 5.0 1.0 3.6 t pzh output enable 1.5 3.5 6.0 0.8 6.5 1.5 6.0 ns t pzl time 1.5 3.6 6.0 1.2 7.9 1.5 6.0 t phz output disable 1.7 3.5 5.6 1.2 7.6 1.7 5.6 ns t plz time 1.7 3.3 5.6 1.0 7.9 1.7 5.6 t a 40 q c to 85 q ct a 40 q c to 85 q ct a 40 q c to 85 q c v cc 4.5v ? 5.5v v cc 4.5v ? 5.5v v cc 4.5v ? 5.5v symbol parameter c l 50 pf c l 250 pf c l 250 pf units 8 outputs switching 1 output switching 8 outputs switching (note 9) (note 10) (note 11) min typ max min max min max f toggle max toggle frequency 100 mhz t plh propagation delay 1.5 5.0 1.5 6.0 2.5 8.5 ns t phl data to outputs 1.5 5.0 1.5 6.0 2.5 8.5 t pzh output enable time 1.5 6.5 2.5 7.5 2.5 10.0 ns t pzl 1.5 6.5 2.5 7.5 2.5 12.0 t phz output disable time 1.0 5.6 (note 12) (note 12) ns t plz 1.0 5.6
5 www.fairchildsemi.com 74abt244 skew note 13: skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of t he same device. the specification applies to any outputs switching high-to-low (t oshl ), low-to-high (t oslh ), or any combination switching low-to-high and/or high-to-low (t ost ). the specification is guaranteed but not tested. note 14: propagation delay variation for a given set of conditions (i.e., temperature and v cc ) from device to device. this specification is guaranteed but not tested. note 15: this specification is guaranteed but not tested. the limits apply to propagation delays for all paths described switching in ph ase (i.e., all low-to-high, high-to-low, etc.) note 16: these specifications guaranteed but not tested. the limits represent propagation delays with 250 pf load capacitors in place of the 50 pf load capacitors in the standard ac load. note 17: this describes the difference between the delay of the low-to-high and the high-to-low transition on the same pin. it is measur ed across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. this specification is guaranteed but not tested. capacitance note 18: c out is measured at frequency f 1 mhz, per mil-std-883, method 3012. t a 40 q c to 85 q ct a 40 q c to 85 q c v cc 4.5v ? 5.5v v cc 4.5v ? 5.5v symbol parameter c l 50 pf c l 250 pf units 8 outputs switching 8 outputs switching (note 15) (note 16) max max t oshl pin to pin skew 0.8 1.8 ns (note 13) hl transitions t oslh pin to pin skew 0.8 1.8 ns (note 13) lh transitions t ps duty cycle 1.0 2.5 ns (note 17) lh ? hl skew t ost pin to pin skew 1.0 2.5 ns (note 13) lh/hl transitions t pv device to device skew 1.5 3.0 ns (note 14) lh/hl transitions symbol parameter typ units conditions t a 25 q c c in input capacitance 5.0 pf v cc 0v c out (note 18) output capacitance 9.0 pf v cc 5.0v
www.fairchildsemi.com 6 74abt244 ac loading *includes jig and probe capacitance figure 1. standard ac test load ac waveforms figure 2. test input signal levels figure 3. test input signal requirements figure 4. propagation delay, pulse width waveforms figure 5. 3-state output high and low enable and disable times figure 6. propagation delay waveforms for inverting and non-inverting functions figure 7. setup time, hold time and recovery time waveforms amplitude rep. rate t w t r t f 3.0v 1 mhz 500 ns 2.5 ns 2.5 ns
7 www.fairchildsemi.com 74abt244 physical dimensions inches (millimeters) unless otherwise noted 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide package number m20b
www.fairchildsemi.com 8 74abt244 physical dimensions inches (millimeters) unless otherwise noted (continued) pb-free 20-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m20d
9 www.fairchildsemi.com 74abt244 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide package number msa20
www.fairchildsemi.com 10 74abt244 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc20
11 www.fairchildsemi.com 74abt244 octal buffer/line driver with 3-state outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide package number n20a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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